1. Field of the Invention
The present invention relates to a semiconductor device having a capacitor, and more particularly to a semiconductor device comprising a capacitor having an MIM (Metal Insulator Metal) structure to be used in a memory cell section.
2. Description of the Background Art
In a semiconductor device, particularly, a dynamic RAM (DRAM), the number of manufacturing steps tends to be increased and a manufacturing time tends to be prolonged with an enhancement in integration and an increase in a capacity. As a solution, the simplification of the manufacturing steps is the most important element.
FIG. 32 is a partial sectional view showing a memory cell region MR and a peripheral circuit region LR such as a logic circuit, a sense amplifier or a decoder which is provided around the memory cell region MR in a conventional DRAM 90.
As shown in FIG. 32, an element isolating film 2 is selectively provided in a main surface of a silicon substrate 1 and the memory cell region MR and the peripheral circuit region LR are defined, and furthermore, an active region AR is defined in each of the memory cell region MR and the peripheral circuit region LR.
In the active region AR of the memory cell region MR, sourcexe2x80x94drain regions 11, 12 and 13 are selectively provided in the surface of the substrate and a gate insulating film 21 is selectively provided between upper parts of edges of the sourcexe2x80x94drain regions 11 and 12 and between upper parts of edges of the sourcexe2x80x94drain regions 12 and 13, and a gate electrode 22 is provided on the gate insulating film 21.
Moreover, a side wall insulating film 23 is provided to cover a side surface of the gate electrode 22 so that an MOS transistor is constituted.
The gate insulating film 21, the gate electrode 22 and the side wall insulating film 23 are also provided on the element isolating film 2 and function as a word line (a transfer gate).
In the active region AR of the peripheral circuit region LR, furthermore, sourcexe2x80x94drain regions 14 and 15 are selectively provided in the surface of the substrate and a gate insulating film 31 is provided between upper parts of edges of the sourcexe2x80x94drain regions 14 and 15. A gate electrode 32 is provided on the gate insulating film 31 and a side wall insulating film 33 is provided to cover a side surface of the gate electrode 32 so that an MOS transistor is constituted.
Then, an interlayer insulating film 3 such as a silicon oxide film is provided to cover the memory cell region MR and the peripheral circuit region LR.
In the memory cell region MR, a bit line 42 is selectively formed in the interlayer insulating film 3 provided on the sourcexe2x80x94drain region 12 and the bit line 42 is electrically connected to the sourcexe2x80x94drain region 12 through a contact plug 41.
In the memory cell region MR, thereafter, a cylindrical lower electrode 52 constituting a cylindrical capacitor is selectively formed on the interlayer insulating film 3 corresponding to upper parts of regions in which the sourcexe2x80x94drain regions 11 and 13 are to be provided. Subsequently, the lower electrode 52 and the sourcexe2x80x94drain regions 11 and 13 are electrically connected through a contact plug 51 provided to penetrate through the interlayer insulating film 3, respectively.
Moreover, a capacitor dielectric film 53 constituted by a dielectric such as Ta2O5 is provided from a surface of the lower electrode 52 between the lower electrodes 52 over the interlayer insulating film 3 formed therearound, and a capacitor upper electrode 54 is provided along a surface of the capacitor dielectric film 53 so that a cylindrical capacitor CP1 is constituted.
An interlayer insulating film 4 is provided over a whole surface to cover the cylindrical capacitor CP1. Flattening is carried out such that main surfaces of the interlayer insulating films 4 are on the level with each other in the memory cell region MR and the peripheral circuit region LR, and an interlayer insulating film 5 is provided on the interlayer insulating film 4.
A wiring layer 72 to be a first wiring layer which is electrically connected to the capacitor upper electrode 54 is selectively provided in a lower main surface of the interlayer insulating film 5 in the memory cell region MR, and a wiring layer 74 is provided in an upper main surface of the interlayer insulating film 5 which is provided above the wiring layer 72 and is electrically connected to the wiring layer 72 through a contact plug 73. The wiring layer 72 and the capacitor upper electrode 54 are electrically connected through a contact plug 71 provided in the interlayer insulating film 4.
Moreover, a wiring layer 62 to be a first wiring layer is selectively provided in the lower main surface of the interlayer insulating film 5 in the peripheral circuit region LR. The wiring layers 62 are formed in regions corresponding to portions provided above the sourcexe2x80x94drain regions 14 and 15, and penetrate through the interlayer insulating films 3 and 4 and are electrically connected to the sourcexe2x80x94drain regions 14 and 15 through a contact plug 61 reaching the sourcexe2x80x94drain regions 14 and 15.
Furthermore, a wiring layer 64 to be a second wiring layer is selectively provided in the upper main surface of the interlayer insulating film 5, and is electrically connected to one of the wiring layers 62 through a contact plug 63. A contact plug 65 penetrating through the interlayer insulating film 5 is connected to the other wiring layer 62.
The wiring layers 62, 64, 72 and 74 and the contact plugs 63, 65 and 73 are constituted by copper (Cu), for example, and the contact plugs 51, 61 and 71 are constituted by tungsten (W), for example.
While an interlayer insulating film and a wiring layer are further formed on the interlayer insulating film 5 in some cases, their illustration and description will be omitted.
As described above, the conventional DRAM 90 comprises the cylindrical capacitor CP1 as a capacitor having an MIM structure. In the formation of the capacitor CP1, the contact plug 51 to be an electrode plug is provided in the interlayer insulating film 3, the capacitor lower electrode 52, the capacitor dielectric film 53 and the capacitor upper electrode 54 are sequentially provided, and furthermore, the contact plug 71 for the connection of the capacitor upper electrode 54 to the wiring layer 72 is formed. Thus, a complicated manufacturing process is required.
It is an object of the present invention to provide a semiconductor device in which a structure of a capacitor is simplified and a manufacturing process is reduced, and a method of manufacturing the semiconductor device.
According to the present invention, a semiconductor device having a multilayer structure includes a capacitor provided in an upper main surface of a first region of an interlayer insulating film, and a wiring layer provided in an upper main surface of a second region of the interlayer insulating film. The capacitor has a capacitor upper electrode provided to be embedded in the upper main surface of the first region of the interlayer insulating film, a capacitor dielectric film provided to cover at least a side surface and a lower surface of the capacitor upper electrode, and at least one lower electrode-and-plug electrically connecting the capacitor to a structure of a layer provided under the capacitor and having a portion inserted in a vertical direction of the capacitor upper electrode, the inserted portion functioning as a capacitor lower electrode, the capacitor dielectric film also covers a surface of the inserted portion of the at least one lower electrode-and-plug, and the wiring layer is electrically connected to a structure of a layer provided under the wiring layer by at least one contact plug having a portion inserted in a vertical direction of the wiring layer.
The capacitor lower electrode also uses as a capacitor contact to be electrically connected to the structure of the lower layer. In the first region, the lower electrode and the capacitor contact can be formed at the same time. Moreover, at least one contact plug to be a contact of the wiring layer in the second region with the structure of the lower layer thereof is also formed at the same time. Consequently, a manufacturing process can be simplified so that a manufacturing cost can be reduced. Furthermore, the capacitor is embedded in the upper main surface of the interlayer insulating film and the capacitor upper electrode can be provided simultaneously with the formation of the wiring layer in the second region by the Single Damascene method. Thus, the manufacturing process can be simplified.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.